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Methodology for Isolating Module Logic Power by Depopulating of Land Grid Array Connector Contacts

IP.com Disclosure Number: IPCOM000098049D
Original Publication Date: 2005-Mar-07
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 175K

Publishing Venue

IBM

Abstract

The implementation of current and future CMOS based technologies for microprocessors (and other high performance multi-function chips) and their ever-increasing power consumption requirements, have presented increased electronic packaging challenges. These challenges are associated with two major areas; (1)the application of an increased number of processor cores and functional units per chip (i.e., as CMOS technology delivers density, but little performance improvements at a given heat flux) and (2) the increase in circuit densities and heat flux per core to gain additional performance improvement, the latter of which unfortunately has yielded technology-based power inefficiencies associated with leakage current (i.e., where, in present technologies, leakage power has been typically on the order of 1/2 of the processor core power). Furthermore, in application, this power either increases rapidly with chip temperature, thereby limiting the usable chip junction temperature (Tj) or has required an increased operating voltage to improve performance. Coupling these factors, excessive burden has been imposed on the module's internal thermal resistance (Rint) requirements and/or on the system's infrastructure (i.e., power, airflow, acoustics, etc.), whereby requiring increased power delivery and/or improved heat removal characteristics to be sized/provided to maximize system performance. In doing so, a less cost-effective system-level packaging and system performance has typically been yielded. In addition, the effort to increase overall chip yields has driven the need for enhanced sigma sort limits and/or the utilization of partial good chips to lower costs (i.e., with one or more bad processing cores or functional units). Although this "sorting" has improved financial returns, it offers minimal system-level power and cooling infrastructure relief due to the aforementioned leakage power associated with the unused core/functional unit (i.e., given the corresponding non-linear reduction in the required power for partial good chips). Given this, a means that minimizes and/or controls these factors are key to improving future overall server packaging density and therefore customer value (i.e., by improving RAS characteristics by lowering chip operating temps or by allowing an increased number of processing units to be packaged within a given system footprint).

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Methodology for Isolating Module Logic Power by Depopulating of Land Grid Array Connector Contacts

The key element of this disclosure is a means to restrict power delivery to partial good chips, thereby maximizing power utilization efficiency. This is accomplished by the strategic de-population of electrical contacts within a land-grid-array connector; an interconnect style typically used to connect today's single-chip (SCM) and Multi-Chip modules (MCM). This depopulation is specifically targeted at the module's bottom surface metallurgy (BSM) connection sites associated with providing power to the bad processor core or unused function (i.e., via the module's substrate). In doing so, power delivery is restricted to this chip location, thereby decreasing the overall required power input & leakage current losses and improving overall power consumption/dissipation efficiency. As depicted below, Fig. 1 provides plane views of the typical LGA attached logic entities. These include the MCM (10) with Integrated Chips (IC) (20), Processor Chip (Cp) Cores (25) & BSM interconnect pads (15), an LGA compatible System Board (40) and a typical LGA connector (50). Note, for the sake of simplicity, the LGA's mechanical actuation hardware has been omitted. Fig. 2 provides a cross-section view of the LGA array attached assembly including the MCM's Cooling cap (60), Processor Chip Thermal Interface (70), Support Frame (80) and the System Board assembly's Insulator (90) and Stiffener (100). These, in conjunction with the appropriate mechanical actuations hardware (omitted), provide the means of completing the electrical connection. Also depicted in Fig. 2 is a typical thermal image of the Cp core (and its associated hot spots) (110). Note, it is the power associated with generating these hot spots as well as the overall chip leakage characteristics that impose the aforementioned performance limitations. Fi...