Browse Prior Art Database

Post-Indicating Latch

IP.com Disclosure Number: IPCOM000098052D
Original Publication Date: 1961-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Heilweil, MF: AUTHOR

Abstract

This circuit is a NOR block set reset latch whose output does not change until after the D. C. set or reset signal is removed. This allows new information to enter into and old information to be read out of the latch at the same time. The latch is shown within the dotted lines. The circuitry outside the dotted lines is added to form a shift register.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 80% of the total text.

Page 1 of 2

Post-Indicating Latch

This circuit is a NOR block set reset latch whose output does not change until after the D. C. set or reset signal is removed. This allows new information to enter into and old information to be read out of the latch at the same time. The latch is shown within the dotted lines. The circuitry outside the dotted lines is added to form a shift register.

Initially, inputs 11 and 12 are positive. Blocks 13 and 14 form a latch, which is in either a set or reset state. In set state, output 15 is positive and output 16 is negative. In reset state, the opposite is true. Assume the latch is in reset state with output 15 negative and output 16 positive. A negative going signal on input 11 deactivates NOR 13, causing output 15 to go positive. Output 15 is cross coupled to NOR 14. Since reset input 12 remains positive, NOR 14 is activated and output 16 goes negative. Output 15 going positive also gates NOR 17. However, as long as input 11 remains negative, no output occurs on line 19. As soon as input 11 goes positive, output 19 goes negative, providing a pulse on input 19 of a latch consisting of NORIs 20 and 21. Therefore, output 22 goes positive and output 23 goes negative.

The circuit is used as a shift register stage by adding NORIs 24 and 26. The input from the previous shift register stage is fed into NOR 24 via line 28. The complement of the input is fed into NOR 26 via line 30. When a positive going shift pulse is applied to input 32, input info...