Browse Prior Art Database

Gate

IP.com Disclosure Number: IPCOM000098058D
Original Publication Date: 1961-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Hilaenrath: AUTHOR

Abstract

This gate circuit includes an Esaki diode 1. It is biased by +V(1) through resistor 3 for bistable operation. A further Esaki diode 2 is biased by +V(2) through resistor 4 for monostable operation.

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Gate

This gate circuit includes an Esaki diode 1. It is biased by +V(1) through resistor 3 for bistable operation. A further Esaki diode 2 is biased by +V(2) through resistor 4 for monostable operation.

A signal applied to terminal 5 switches diode 1 from its low voltage to its high voltage stable state. The increase of voltage across diode 1 is applied through resistor 6 to the biasing circuit of diode 2. This diode is now biased for bistable operation. When diode 2 is so biased, input signals applied to terminal 7 switch it from one stable state to the other to provide output signals at terminal 8.

When no gate signal is applied to terminal 5, diode 1 remains in its low voltage stable state so that diode 2 remains biased for monostable operation. When diode 2 is in this condition, it is not switched by input signals applied to terminal 7 and no output signals appear at terminal 8.

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