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Unijunction Transistor Trigger

IP.com Disclosure Number: IPCOM000098059D
Original Publication Date: 1961-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Lord, HR: AUTHOR [+2]

Abstract

The trigger circuit employs a unijunction transistor 10 and a pulse transformer 11 to obtain a logical storage capability.

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Unijunction Transistor Trigger

The trigger circuit employs a unijunction transistor 10 and a pulse transformer 11 to obtain a logical storage capability.

The operation depends on the combination of the negative resistance characteristic of transistor 10 and the phase reversing capability of transformer
11.

When the power VS is on, the trigger assumes the off condition and the output is at its up level, approximately VL. To change the state of the trigger, a positive going pulse is applied to terminal 12. By induction, this pulse appears at the transformer 10 secondary 13 and is applied to the emitter 14 of the unijunction transistor 10 to switch it through the negative resistance region to its second stable state. The output assumes the down level, or on condition. A positive going pulse at terminal 15 returns transistor 10 to its first stable state.

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