Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Variable Clock Pulse Generator

IP.com Disclosure Number: IPCOM000098085D
Original Publication Date: 1961-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Notz, WA: AUTHOR

Abstract

The device generates two non-overlapping clock signals. The logical diagram (top) consists of ten gate pairs L1... L10. Each pair L1... L10 has two logical gates, each either an AND or OR. Each logical gate has one or more inputs and an output. The output of a gate is active when the input or inputs fulfill the conditions specified by the gate designation. For example, the gate 10 activates its output 11 when both inputs 12 and 13 are active. One and only one output of each pair L1...L10 is always active. When the inputs turn one of the outputs on, the other output turns off. However, particular outputs are held active by external control irrespective of input signals to the particular pair.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Variable Clock Pulse Generator

The device generates two non-overlapping clock signals. The logical diagram (top) consists of ten gate pairs L1... L10. Each pair L1... L10 has two logical gates, each either an AND or OR. Each logical gate has one or more inputs and an output. The output of a gate is active when the input or inputs fulfill the conditions specified by the gate designation. For example, the gate 10 activates its output 11 when both inputs 12 and 13 are active. One and only one output of each pair L1...L10 is always active. When the inputs turn one of the outputs on, the other output turns off. However, particular outputs are held active by external control irrespective of input signals to the particular pair.

By selectively holding the top output of certain of the circuits continually active, the clock switches through any one of three sequences: (1) L1, L2, L7, L8, L1, L2, etc.

(2) L1, L3, L6, L7, L8, L1, L3, etc.

(3) L1, L4, L5, L6, L7, L8, L1, L4, L5, etc.

Sequence 1 is obtained when L3 and L4 top outputs are held continuously active. Sequence 2 is obtained when the L2 and L4 top outputs are held continuously active. Sequence 3 is obtained when the L2 and L3 top outputs are held continuously active.

An external clock signal on line 47 is used to synchronize the ring circuit with some external pulse source when the circuit is operating in sequence 3. With two OR's in L4, the ring is free-running in sequence 3. The absence of a signal on line 13 stops the ring. Output 48 is turned on by the coincidence of signals from the L7 top output and from the L8 bottom output. Output 49 is turned on by the coincidence of signals from the L7 bottom output and on the L8 top output. Output 48 is turned off by either a signal on the L7 bottom output or by a signal on the L8 top output. Likewise, output 49 i...