Browse Prior Art Database

Memory

IP.com Disclosure Number: IPCOM000098087D
Original Publication Date: 1961-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Sanborn, JL: AUTHOR

Abstract

Memory bit positions A, B, C and D each have a persistent current loop A5...D5, an input cryotron A6...D6 and an output cryotron A7...D7. Each cryotron A6...D6 and A7...D7 has three control lines. The arrows on the cryotron control lines indicate that the magnetic field produced by one of the control lines is in opposition to the field produced by the other two control lines. To make any one cryotron gating element resistive, two conditions are necessary. First, the two controls which produce fields in the same direction must be active. Second, the one control which produces a field opposite to the other two controls must not be active.

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Memory

Memory bit positions A, B, C and D each have a persistent current loop A5...D5, an input cryotron A6...D6 and an output cryotron A7...D7. Each cryotron A6...D6 and A7...D7 has three control lines. The arrows on the cryotron control lines indicate that the magnetic field produced by one of the control lines is in opposition to the field produced by the other two control lines. To make any one cryotron gating element resistive, two conditions are necessary. First, the two controls which produce fields in the same direction must be active. Second, the one control which produces a field opposite to the other two controls must not be active.

In order to write a ""1 into any particular bit position, current is applied to the write and W lines in the entire memory array. Current is then selectively applied to one Y line and removed from one X line. A persistent current is stored in the particular bit position which is at the intersection of the Y line to which current is applied and the X line from which current is removed.

Information is read from any particular bit position by selectively applying current to one Y line and selectively removing current from one X line. Resistance is introduced into the S line, if the cell which is at the intersection of the altered X and Y lines has a persistent current stored in it.

The array lends itself to close packing. It has a minimum of return current paths which pass through the memory array. The write lines need no retu...