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Card Reader Tester

IP.com Disclosure Number: IPCOM000098124D
Original Publication Date: 1960-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Murray, RF: AUTHOR [+2]

Abstract

This is a method for testing card reader 1 which normally sends successive three-word messages into CPU 2 by way of sections A, B and C of buffer register 3. A test card in which the first bit of each word is a parity bit for the remaining word bits is inserted in reader 1. Apparatus in operator console 4 is manually operated to send a start pulse through normally conditioned gate 5 to shift flip flops 6 and 7 to their 1 state. This This action conditions gates 8, 9, 10 and 11 and deconditions gates 5, 15 and 17. The same start pulse also is transmitted over conductor 12 to start card reader 1. Test word messages from 1 are then sent into sections A, B and C of register 3.

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Card Reader Tester

This is a method for testing card reader 1 which normally sends successive three-word messages into CPU 2 by way of sections A, B and C of buffer register
3. A test card in which the first bit of each word is a parity bit for the remaining word bits is inserted in reader 1. Apparatus in operator console 4 is manually operated to send a start pulse through normally conditioned gate 5 to shift flip flops 6 and 7 to their 1 state. This This action conditions gates 8, 9, 10 and 11 and deconditions gates 5, 15 and 17. The same start pulse also is transmitted over conductor 12 to start card reader 1. Test word messages from 1 are then sent into sections A, B and C of register 3.

If a parity error is detected, register 3 sends error indicating pulses through appropriate ones of now conditioned gates 10 and 11, OR circuit 13, and conductor 14 to stop card reader 1. In all cases, the word available pulse generated by register 3 which normally passes over conductor 19 to CPU 2-is now blocked by deconditioned gate 15. If CPU 2 tries to select card reader 1 while a test is going on, the select pulse normally passed to CPU 2 over conductor 16 is blocked at deconditioned gate 17. Instead, the select pulse is re- routed through conditioned gate 9 and conductor 18 to an appropriate section of CPU 2 to indicate that card reader 1 is not available. In order to end test mode operation, another pulse from console 4 is sent through gate 8 to shift flip flops 6 and...