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A Core MQ And Shift Register

IP.com Disclosure Number: IPCOM000098140D
Original Publication Date: 1960-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Frush, DI: AUTHOR

Abstract

This MQ and shift register accomplishes incrementing and decrementing without use of an adder in multiplying and dividing operations, for example. A shift register 12 may be selectively shifted in either direction or read out of in parallel under control of the register control and drivers. An M out of N coded input is translated into a decimal code and is applied to the register 12 to set the one appropriate stage on.

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A Core MQ And Shift Register

This MQ and shift register accomplishes incrementing and decrementing without use of an adder in multiplying and dividing operations, for example. A shift register 12 may be selectively shifted in either direction or read out of in parallel under control of the register control and drivers. An M out of N coded input is translated into a decimal code and is applied to the register 12 to set the one appropriate stage on.

Each decrementing pulse applied through and circuit 13 shifts the bit in the register until there is no output from any of the parallel outputs from the register. A sense latch on the right hand end of the register senses when a bit is shifted out of the register and may be used to control multiplication shifts. A 6, for example, entered in the register is decremented by successively shifting the bit from the 6 position to the right. The decremented or incremented value may be read out at any time from the M out of N latches.

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