Browse Prior Art Database

Solid State Decoder

IP.com Disclosure Number: IPCOM000098143D
Original Publication Date: 1960-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Constantine, G: AUTHOR

Abstract

Bistable magnetic cores are employed to steer current through any one of 2/n/ output circuits in accordance with an n bit binary input code.

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Solid State Decoder

Bistable magnetic cores are employed to steer current through any one of 2/n/ output circuits in accordance with an n bit binary input code.

As shown, the decoder employs two cores for each input bit position. The upper core of each pair represents a bit value of 1 and the lower core represents a bit value of 0. Each output circuit is wound in series through one core of each pair, the sense of the windings all being such as to present high impedance to current flow when the associated cores are in a reset state. There is a different output circuit for each combination of the input code.

To perform a decoding operation, the control winding of one core of each pair is energized, in accordance with a given input code combination, to drive the associated core to the set, or low impedance state. The output driver is then activated to send current through the output circuits. The current is steered through the one circuit, all the cores of which are in the low impedance state. All cores are reset between decoding operations.

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