Browse Prior Art Database

Buffer System

IP.com Disclosure Number: IPCOM000098151D
Original Publication Date: 1960-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Skov, RA: AUTHOR [+2]

Abstract

The device illustrated is a buffer system, used in conjunction with a synchronous output device, which buffer adjusts the data input rate in such a manner as to maintain the buffer half filled.

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Buffer System

The device illustrated is a buffer system, used in conjunction with a synchronous output device, which buffer adjusts the data input rate in such a manner as to maintain the buffer half filled.

The drawing shows a tape unit 10 which, due principally to motor speed variations, reads seven channel tape at a rate which deviates slightly from the rate at which it is desired to transmit the data to a synchronous unit 11. The seven channel data are read into the seven channels of a core matrix buffer 12 which, for the purpose of illustration, can store six seven bit characters. A motor 13 in the tape unit 10 rotates capstan 14 to move the seven channel tape 15 between reels 16 and 17. Seven magnetic heads 18 read the data from tape 15 and transfer the information over a data bus to AND circuits 19. From 19 the data are gated to row drivers 21 under control of a readin gate pulse on lead 20.

The energized row drivers 21 apply half select pulses to the corresponding rows of buffer 12. A selected column driver 23 applies a half select pulse via lead 22 to the corresponding column of buffer 12. Thus, each seven bit character is stored in any one of the six columns of buffer 12 dependent upon which of the drivers 23 is selected. Selection of drivers 23 is controlled by a six stage readin counter 24 whose stages are turned ON sequentially. The one stage that is ON conditions a corresponding AND circuit 25 to pass the readin pulse on lead 26 to the selected driver 23. The readin gate starts earlier than the readin pulse, but with sufficient overlap to allow the two half select pulses from drivers 21 and 23 to selectively set a vertical row of cores.

Readout from buffer 12 is under control of a six stage readout counter 27 which operates in a similar manner to readin counter 24. Its one stage which is ON, in conjunction with a readout pulse on lead 28, produces an output from one of the corresponding AND circuits 29 to operate one of the readout drivers 30 and to apply a full select pulse to the corresponding lead 31. The outputs from buffer 12 are sensed on the sense leads 32, and are fed through the sense amplifiers 33 to AND circuits 34. AND circuits 34 are selectively operated by the readout gate pulse on lead 34a to cause the data to be applied via an output data bus to unit 11. The readout gate and readout pulse also overlap in time.

The readin and readout operations are under control of a seven stage clock 35 and a pulse generating circuit. The latter, upon receiving a start pulse, generates seven different pulses sequentially and then returns to home position. It remains at home position until it receives either a readin or readout request from the tape unit 10 and the synchronous unit 11. The complete cycle of clock 35 is short in comparison to the average time between characters read from the tape unit and, therefore, clock 35 goes through both a readin and a readout cycle well within the time between characters. At the...