Browse Prior Art Database

Core Translator And Multiplier

IP.com Disclosure Number: IPCOM000098152D
Original Publication Date: 1960-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Rauhe, ML: AUTHOR

Abstract

Code translation and multiplication are realized in a single magnetic core array. An input code on the 1, 2, 4, 8 and X input lines sets a selected one of the cores depending upon which of the switches 1N, 2N or 3N is closed.

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Core Translator And Multiplier

Code translation and multiplication are realized in a single magnetic core array. An input code on the 1, 2, 4, 8 and X input lines sets a selected one of the cores depending upon which of the switches 1N, 2N or 3N is closed.

With switch 1N closed, the various input code combinations set corresponding cores from 0 to 9, so that outputs are provided on the corresponding 0 to 9 output lines and on the No Carry line. With switch 2N closed, the input code combinations set the cores corresponding to two times the decimal equivalent of the input code, and a Carry 1 signal for output signals, greater than 10 plus the units order digit value, is supplied from the outputs. With switch 3N closed, output values equal to three times the decimal equivalent of the input are provided, as well as No Carry, Carry 1 or Carry 2 signals. After each input translation, the cores are reset by a common reset line.

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