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High Speed Inverting Level Setter

IP.com Disclosure Number: IPCOM000098210D
Original Publication Date: 1960-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR [+3]

Abstract

The circuit is a non-saturating inverter providing a level shift at its output.

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High Speed Inverting Level Setter

The circuit is a non-saturating inverter providing a level shift at its output.

The germanium diodes at the input of the transistor are logic diodes. The transistor is connected in the common emitter configuration so that inversion of the input to the base is provided at its collector. The Zener diode is connected in series between the positive and negative sources which are so proportioned that the diode is continually conducting in its reverse direction. This provides a constant fixed voltage drop between the collector of the transistor and the output terminal.

The silicon diodes connected between the output terminal and the base provide degenerative feedback to keep the transistor out of saturation. The voltage drop across the two silicon diodes provides a threshold voltage so that they are rendered conductive prior to saturation of the transistor. This then decreases the base drive sufficiently to maintain the transistor below saturation.

The voltage translation effected by the Zener diode allows the output terminal to connect directly to an input diode of a succeeding stage without intervening coupling networks. The non-saturating feature increases the switching speed of the circuit by eliminating delays due to minority carrier storage. The PNP counterpart of the circuit can be fabricated by suitably reversing bias potential and diode polarities.

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