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Multiple Ring, Sum Logic Unit

IP.com Disclosure Number: IPCOM000098214D
Original Publication Date: 1960-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Leightner, RA: AUTHOR

Abstract

Comparison is made between two numbers such that if they are equal to each other, no output is obtained, and conversely, a difference in numbers produces an output. Each of the two numbers consists of a set of bits with up and down levels. For one number, the up level is a positive voltage representing a 1 and the down level or 0 is at ground. The other number is the reverse; an up level represents a 0 and the down level is a 1. A 1 in each bit position to be compared causes full signal voltage to appear across the divider network R(1), R(2). Assuming 20 volts across the two equal resistors, then 10 volts appears at their mid-point. A 0 in each bit position to be compared causes the same 10 volts to appear at the mid-point. A combination of 1 and 0 volts causes either 20 or 0 volts to appear at the mid-point.

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Multiple Ring, Sum Logic Unit

Comparison is made between two numbers such that if they are equal to each other, no output is obtained, and conversely, a difference in numbers produces an output. Each of the two numbers consists of a set of bits with up and down levels. For one number, the up level is a positive voltage representing a 1 and the down level or 0 is at ground. The other number is the reverse; an up level represents a 0 and the down level is a 1. A 1 in each bit position to be compared causes full signal voltage to appear across the divider network R(1), R(2). Assuming 20 volts across the two equal resistors, then 10 volts appears at their mid-point. A 0 in each bit position to be compared causes the same 10 volts to appear at the mid-point. A combination of 1 and 0 volts causes either 20 or 0 volts to appear at the mid-point.

Diodes D(1) and D(2) are steering diodes. Transistors T(1) and T(2) are biased at 10 volts so that equal bits in each position do not cause either transistor to conduct. An unbalance causes one transistor or the other to conduct, depending upon whether the signal to the divider is both at the high or low voltage level. Conduction of either T(1) or T(2) causes an output signal. Transistor T(3) is an inverter to correct for the output phase of the diode steering circuit.

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