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Diode Switching Binary Trigger

IP.com Disclosure Number: IPCOM000098251D
Original Publication Date: 1960-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Morris, EF: AUTHOR

Abstract

The binary trigger utilizes diode logic in a sequential switching arrangement. The AND and OR blocks are conventional diode logic circuits and the emitter followers are conventional transistor circuits for providing power gain. The level setters are transistor current switching blocks which restore voltage levels and provide complementary outputs.

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Diode Switching Binary Trigger

The binary trigger utilizes diode logic in a sequential switching arrangement. The AND and OR blocks are conventional diode logic circuits and the emitter followers are conventional transistor circuits for providing power gain. The level setters are transistor current switching blocks which restore voltage levels and provide complementary outputs.

At time t(1) (lower drawing) the S input is down and bar S is up. The X output is down and is latched in this condition by the feedback loop including A(1) and O(2) and the loop including A(2), A(3), O(1) and A(5). The Y output is also down and is held in that condition by the circuit including A(3), A(4), O(1), A(6) and O(3).

When S rises, the output of O(1) rises and is applied to A along with the already up input from Q. 0(2), therefore, switches to provide a positive X output, bar X going negative. No change occurs at Y since S has fallen while X has risen and no change is produced at A(4). The circuit is now at the condition shown at t(2). When S falls, the output of A(3) falls. However, the outputs of 0(1), A(1) and 0(2) are held up by virtue of the now positive S and the positive X. Thus, X is latched in this condition. At the same time, A(4) is switched producing a positive output at 0(3) which raises the Y output. The now negative bar Y is fed back to A(5) to lower its output, but 0(2) is held up by the output of A(1). This is the condition at t(3).

When S rises again, the output...