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Binary Trigger

IP.com Disclosure Number: IPCOM000098252D
Original Publication Date: 1960-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Morris, EF: AUTHOR

Abstract

The circuit is a binary trigger using one type of transistor and requiring only one level of delay to switch states.

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Binary Trigger

The circuit is a binary trigger using one type of transistor and requiring only one level of delay to switch states.

The circuit is composed of three current switching blocks and uses the third level logical technique in which one input signal has a swing of a magnitude to render a particular transistor of a logical block conductive to the exclusion of the other transistors of the same block. This third level or extended voltage swing is generated by the coupling network R(3), R(4), V(4) which provides the third level input to transistor T(4). Standard input swings are generated by the coupling networks R(1), R(2), V(4).

At time t(0) (lower drawing) the X input is negative and bar X is positive. The X input renders T(4) conductive to the exclusion of T(5) and T(6). Therefore, the collectors of T(5) and T(6) tend to assume their negative levels. The Y output is thus at its negative level. Similarly, T(6) is held non-conducting and the Z output is negative. The Y and Z levels are fed back to T(2) and T(9), respectively, rendering both transistors conductive. The Zener diodes Z(1), Z(2) translate the output voltages to suitable input levels.

When X goes positive, T(4) is cut off. At the same time, bar X goes negative, rendering T(1) and T(8) conductive. T(5) is rendered conductive by the negative Z output fed back to its base, raising its collector to its positive level and providing a positive Y output. Since T(5) is conducting, T(6) is cut off, prov...