Browse Prior Art Database

Current Switching Shift Register

IP.com Disclosure Number: IPCOM000098253D
Original Publication Date: 1960-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Morris, EF: AUTHOR

Abstract

Three level current switching logic techniques are applied to produce a hazard-free shift register requiring a single shift pulse and using a minimum of components.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 92% of the total text.

Page 1 of 2

Current Switching Shift Register

Three level current switching logic techniques are applied to produce a hazard-free shift register requiring a single shift pulse and using a minimum of components.

Assume initially that a 0 is stored in the stage and that a 1 is read into it from the preceding stage when the shift pulse rises. The input to T(1) is positive and the input to T(5) is negative, holding both of these transistors off. At this time T(2) is conducting, providing a positive level to the base of T(6) which renders this transistor conducting.

As the shift pulse rises, a third level or inhibiting input is applied to the base of T(5). This input is more positive than the input to T(6), and T(5) conducts, cutting off T(6). The collector of T(6) goes positive, cutting off T(2) and T(8). T(6) is latched in its off state by T(2) whose collector is now at a negative level. The output remains unchanged since T(9) is conductive. This holds off T(10), providing a negative level at the emitter of the transistor T(11).

When the shift pulse falls, T(5) is turned off, allowing T(4) to conduct. The output of T(4) goes negative and is coupled by the third level networks to the basis of T(3) is rendered conductive which prevents conduction of T(1) should the input signal now change. T(7) also conducts, shutting off T(9) and providing a positive level at the emitter of T(11). The latter transistor is cut off and the output goes positive, indicating 1 entered in the stage.

Th...