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Pluggable Transistor Level For Q-PAC

IP.com Disclosure Number: IPCOM000098295D
Original Publication Date: 1960-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Young, WM: AUTHOR

Abstract

In a pluggable unit package, circuit components 3, shown in a cutaway section, are assembled in layers between circuit pins 1 by connecting component leads 2 to the circuit pins. After assembly of the components the assembly is potted in a suitable potting compound. Transistors 4 are secured to pluggable level 5 having a number of sockets molded in its periphery allowing circuit pins to be inserted into and make electrical contact with the sockets.

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Pluggable Transistor Level For Q-PAC

In a pluggable unit package, circuit components 3, shown in a cutaway section, are assembled in layers between circuit pins 1 by connecting component leads 2 to the circuit pins. After assembly of the components the assembly is potted in a suitable potting compound. Transistors 4 are secured to pluggable level 5 having a number of sockets molded in its periphery allowing circuit pins to be inserted into and make electrical contact with the sockets.

The leads of transistors 4 are connected to the sockets. Diodes may be secured to the underside of pluggable level 5 or may be secured to the main potted unit. The pluggable level may be removed from the potted main package and the unit having a defective component can be replaced.

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