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Three Stable State Count Down Circuit

IP.com Disclosure Number: IPCOM000098299D
Original Publication Date: 1960-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Leightner, RA: AUTHOR

Abstract

A transistorized circuit is provided for dividing an input pulse train by three. The circuit utilizes three NPN grounded emitter transistors 10, 11 and 12 in three individual stabilized pulse amplifiers A, B, C which are interconnected to provide ring symmetry. The collector load resistances 13, 14 and 15 each feed two transistors through diode ring 16A-16B, 17A-17B, 18A-18B. This configuration gives a voltage drop across two load resistances at all times, even though only one transistor is conducting at a time.

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Three Stable State Count Down Circuit

A transistorized circuit is provided for dividing an input pulse train by three. The circuit utilizes three NPN grounded emitter transistors 10, 11 and 12 in three individual stabilized pulse amplifiers A, B, C which are interconnected to provide ring symmetry. The collector load resistances 13, 14 and 15 each feed two transistors through diode ring 16A-16B, 17A-17B, 18A-18B. This configuration gives a voltage drop across two load resistances at all times, even though only one transistor is conducting at a time.

Assume at initiation that transistor 10 starts conducting. Its collector voltage drops to 0 volts, thus biasing transistors 11 and 12 to cutoff through resistors 19 and 20, respectively. The first positive input pulse finds a path through diode 21 and capacitor 22 and turns on transistor 12. Diodes 23 and 24 are back biased due to the voltage at the collectors of transistors 11 and 12. With 12 conducting, transistors 10 and 11 are biased off through resistors 25 and 19, respectively.

The next incoming pulse turns on transistor 11 through diode 24 and capacitor 26 and turns off transistor 12. The third pulse turns on transistor 10 and turns off transistor 11. With the output line connected to the collector of transistor 10, an output pulse is produced. Thus, a single output pulse is obtained for every three input pulses.

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