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Browse Prior Art Database

Magnetic Core Switching System

IP.com Disclosure Number: IPCOM000098306D
Original Publication Date: 1960-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Hohl, JH: AUTHOR

Abstract

The multi branch magnetic core switching system represents a parallel shift register comprising a plurality of bit storage positions in each stage. The transfer of the bit pattern from a stage R over an auxiliary stage S to a stage T is achieved in two steps by switching pulses controlled by the impedance of the core windings depending on the state of remanence of the respective cores.

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Magnetic Core Switching System

The multi branch magnetic core switching system represents a parallel shift register comprising a plurality of bit storage positions in each stage. The transfer of the bit pattern from a stage R over an auxiliary stage S to a stage T is achieved in two steps by switching pulses controlled by the impedance of the core windings depending on the state of remanence of the respective cores.

Assume that a bit pattern, 1, 1, 0, 0, 0 represented by the ONE and ZERO states of the respective cores 11 to 15 of stage R, is to be transferred to stage S and that all cores 16 to 20 are preset in the ZERO state. By applying a pulse between terminals A and B of such polarity that it tends to switch the cores into the ONE state, the current produced by the pulse will branch and tend to flow through all the parallel paths linking cores 11 to 15. The actual current flow is dependent upon the state of remanence of the respective cores. The current through the low impedance windings of cores 11 and 12 which are in the ONE state is larger than the current through the high impedance windings of the cores 13 to 15 which are in the ZERO state. By means of the higher current passing through the control windings of cores 16 and 17, the latter are. switched over towards the ONE condition and cores 18, 19 and 20 are not switched.

In the starting condition for the second transfer step, all the cores 21 to 25 of stage T are preset to the ONE condition. A pulse bet...