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Skewed Memory Readout

IP.com Disclosure Number: IPCOM000098313D
Original Publication Date: 1960-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Felton, BC: AUTHOR [+2]

Abstract

A computer can take advantage of skew if the outputs from memory planes are treated in a preferential manner, that is, those uppermost planes in a memory array are read out first which contain bits of information that are required first by the computer, and those bits in memory that are required last by the computer are read out from the lowermost memory planes.

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Skewed Memory Readout

A computer can take advantage of skew if the outputs from memory planes are treated in a preferential manner, that is, those uppermost planes in a memory array are read out first which contain bits of information that are required first by the computer, and those bits in memory that are required last by the computer are read out from the lowermost memory planes.

An operand register OR stores an instruction word of 50 bits (48 bits + 2 parity bits). Each bit or groups of bits in the instruction register is assigned a specific function. The sign bit tells if the data in the register are in true or complement form. Bits 1..6 refer to the instruction class and variations. Bit 7 is a spare and bits 8..23 are instruction modifiers. Bit 24 refers to double indexing, bit 25 to indirect addressing, bits 26..29 relate to index selection and bits 30..47 relate to the address. The bits required first by the computer are read out at the head of the skew (the uppermost planes of a memory array), and readout continues with delay due to skew being employed, rather than corrected for, to deliver data in a preferential manner to the computer.

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