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Double Trigger

IP.com Disclosure Number: IPCOM000098343D
Original Publication Date: 1960-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR

Abstract

The circuit produces two voltage outputs A and B, representative of the first and second digits respectively of a binary count 00, 01, 10 and 11. In response to input signals, the circuit advances repetitively through the counts zero, one, two and three.

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Double Trigger

The circuit produces two voltage outputs A and B, representative of the first and second digits respectively of a binary count 00, 01, 10 and 11. In response to input signals, the circuit advances repetitively through the counts zero, one, two and three.

Inputs designated x and (bar x) are complements of each other. Each output A and B represents a 0 in the off condition and a 1 in the on condition. As input x is sequentially pulsed, output A progresses through the states 0, 1, 0, 1, while output B progresses through states 0, 0, 1, 1. Hence, successive inputs activate the A and B outputs sequentially through counts zero, one, two and three, by the binary output notations 00, 01, 10 and 11.

The circuit consists of combinations of AND and OR logical blocks interconnected to form latch circuits. The left hand terminals of the blocks are input terminals. The right hand terminals are output terminals. In each block which has two output terminals, one is always UP while the other is DOWN. As an example, the on state of OR 12 is represented by the terminal 4 being UP, the output being designated a. The off state is represented by the terminal 3 being UP, the output being designated (bar a). Similar designations are used with respect to the outputs of other blocks.

The following Boolean equations describe the operation of the circuit:. A=(bar x)a + x(bar c)

B=x(bar b)ca+ (bar c)b +(bar a)b +(bar x)b

Each latch consists of one or more AND blocks in combina...