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Browse Prior Art Database

Capacitor Delay Circuit

IP.com Disclosure Number: IPCOM000098393D
Original Publication Date: 1960-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Lee, EL: AUTHOR

Abstract

This is a transistor delay circuit in which a capacitor is used to hold a charge for a predetermined length of time to shift the input through a specified delay.

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Capacitor Delay Circuit

This is a transistor delay circuit in which a capacitor is used to hold a charge for a predetermined length of time to shift the input through a specified delay.

The input at terminal 18 is the clock, and the input at terminal 10 is the information to be shifted. With the circuit in operation, capacitor 12 is charged to +V at terminal 13 minus the Zener voltage of Zener diode 15. The first bit of information at terminal 10 turns on transistor 11. With transistor 11 conducting, capacitor 12 charges rapidly from a source +V at terminal 13 through diode 14, Zener diode 15 and transistor 11. At the next clock pulse at 18, the Zener diode 15 conducts in the forward direction and the capacitor 12 discharges rapidly through resistor 17 and inductance 21, giving an output pulse at terminal 20. This pulse at 20 represents the input shifted in time by the difference between input pulse time and clock pulse time. The delay may be increased by cascading a number of circuits together.

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