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Pulse Circuit Using Avalanche Techniques

IP.com Disclosure Number: IPCOM000098394D
Original Publication Date: 1960-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Waxman, R: AUTHOR

Abstract

This circuit supplies either a low impedance series load requiring a high speed, high current pulse of variable pulse width or any high impedance parallel load requiring a high speed, high voltage pulse of variable width.

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Pulse Circuit Using Avalanche Techniques

This circuit supplies either a low impedance series load requiring a high speed, high current pulse of variable pulse width or any high impedance parallel load requiring a high speed, high voltage pulse of variable width.

The circuit is operated with both transistors T1 and T2 in the avalanche region, but with transistor T2 ordinarily being cut off by the potential applied to its base and with T1 self biased off. A trigger pulse applied to the base of T1 moves the operating point on its A. C. load line to an unstable portion of the Ib constant characteristic causing T1 to avalanche.

This action effectively raises the emitter potential of T1 from ground towards V1 without T1 saturating, causing a high potential negative pulse to be applied to the base of T2. This overdrives T2 far into its saturation region, causing a fast rise time, high potential output pulse from the collector of T2. The variable resistor R3 controls the amount of overdrive to T2 which in turn determines the storage time of the carriers and thus shapes the current pulse and determines the pulse width.

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