Browse Prior Art Database

Two Core, Two Transistor Per Bit Counter

IP.com Disclosure Number: IPCOM000098404D
Original Publication Date: 1960-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Seelbach, WC: AUTHOR

Abstract

The binary counter, capable of accepting input signals of either polarity, comprises a plurality of stages in which each stage has two bistable magnetic cores and two transistors.

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Two Core, Two Transistor Per Bit Counter

The binary counter, capable of accepting input signals of either polarity, comprises a plurality of stages in which each stage has two bistable magnetic cores and two transistors.

Assume cores C1 and C2 are initially in the 0 state and cores C1A and C2A are initially in the 1 state and that a pulse of either polarity energizes the input of the counter. One of the cores C1 or C1A starts switching from its initial stable state toward an opposite stable state inducing a voltage on one of the output windings 10. Such action causes T1 to conduct providing blocking oscillator type action to take place to switch both cores C1 and C1A to opposite stable states.

A second pulse of either polarity energizing the input causes one of the cores C1 or C1A to start switching back toward its original stable state. This induces an opposite voltage on one of the output windings 10 which turns T2 on. The transistor T2 in turning on resets both cores C1 and C1A back to their original states of magnetization and provides an input to the next stage of the counter.

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