Browse Prior Art Database

Memory Drive System

IP.com Disclosure Number: IPCOM000098405D
Original Publication Date: 1960-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

McDonnell, JA: AUTHOR

Abstract

Transfer circuits of a shift register are employed to drive core matrices sequentially. T1, T2 and T3 represent the transfer circuits of the shift register comprised of four stages S1 through S4.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Memory Drive System

Transfer circuits of a shift register are employed to drive core matrices sequentially. T1, T2 and T3 represent the transfer circuits of the shift register comprised of four stages S1 through S4.

A portion of the matrix comprises three columns of cores threaded with horizontal wires coded 0, 1, 2, 3 and 6. These are selectively energized to provide half-select currents as the transfer circuits are sequentially energized with half-select currents during operation of the shift register.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]