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Phase Alternating Status Keeper

IP.com Disclosure Number: IPCOM000098427D
Original Publication Date: 1960-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Trapnell, FM: AUTHOR [+2]

Abstract

The system selects the next slot in sequence from a band of sequential data word slots on a drum in which data may be recorded or read. The band of word slots begins at an index point on the drum. Associated with the word band is a status track having, for each word slot, a corresponding status bit storage area for indicating the data status in the related slot. The status track is used to find the correct location for the next read-write operation (word slot). The status keeping system alternately reads and writes in each successive status bit position. Whether the system reads or writes in the odd positions is determined by a trigger stored status phase bit whose state alternates on each cycle of operation. The system continues to read and write 1's in the status track until a 0 is first detected on a read cycle.

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Phase Alternating Status Keeper

The system selects the next slot in sequence from a band of sequential data word slots on a drum in which data may be recorded or read. The band of word slots begins at an index point on the drum. Associated with the word band is a status track having, for each word slot, a corresponding status bit storage area for indicating the data status in the related slot. The status track is used to find the correct location for the next read-write operation (word slot). The status keeping system alternately reads and writes in each successive status bit position. Whether the system reads or writes in the odd positions is determined by a trigger stored status phase bit whose state alternates on each cycle of operation. The system continues to read and write 1's in the status track until a 0 is first detected on a read cycle. Then, data are recorded in the next word slot position and the status keeping is discontinued until the next required operation. The status phase bit, initially stored in Status Bit Trigger 12, is complemented at the beginning of each operation.

In the circuitry the drum index pulse is gated through AND 10 at the start of the status seeking operation. The Status Phase Trigger 11 is either set or reset dependent upon the state of trigger 12 as effective through AND's 13 and 14. Trigger 11 is then switched at each valid word slot position by a valid location signal applied through AND 15 to trigger 11. Triggering 11 condit...