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Half Cycle Register

IP.com Disclosure Number: IPCOM000098442D
Original Publication Date: 1960-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Bedrij, OJ: AUTHOR [+2]

Abstract

The circuit is one position of a serial accumulator, using alternate register gating, for telescoping into a single interval the time necessary to transfer data to and from the registers.

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Half Cycle Register

The circuit is one position of a serial accumulator, using alternate register gating, for telescoping into a single interval the time necessary to transfer data to and from the registers.

The operation is shown by the example in the table.

SEE ORIGINAL FOR TABLE

Gates G1, G4, G6 and G7 are simultaneously operated by an A level. Gates G2, G3, G5 and G8 are simultaneously operated by an A level. A first bit is entered into register R1 through gate G3, during gating level bar A. A second bit is entered into R2 through G4 during A, while simultaneously the first bit is entered into R3 via G1 and the adder through G7 and OR1. Thereafter, whenever R1 receives a bit, R2 transmits one, and vice versa. Similarly, R3 and R4 are alternately gated to loop bits through the adder.

Each group of two gates and one register, e.g., G1, G5 and R3, may be constructed as shown in Vol.2 No.6, IBM Technical Disclosure Bulletin, April 1960, page 50.

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