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Translator Circuit

IP.com Disclosure Number: IPCOM000098449D
Original Publication Date: 1960-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ross, HN: AUTHOR

Abstract

Cores B-1 and B-0 are included in a translator circuit for developing an internal bias to provide a distinctive output on the single sense line which matches an applied code pattern.

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Translator Circuit

Cores B-1 and B-0 are included in a translator circuit for developing an internal bias to provide a distinctive output on the single sense line which matches an applied code pattern.

Transformer cores C-1 and C-0, which represent the 2/1/ and 2/0/ positions of a binary coded representation to be decoded, are pulsed in a one or zero direction by the drivers D-1 and D-0. As a result, an output is available on a single one of the sense lines 00, 01, 10, or 11, which corresponds to the applied bit configuration from D-1 and D-0.

Each sense line includes a number of individual windings which are uniquely wound on C-1 and C-0 in either a zero direction, or a one direction. A positive potential is developed in zero windings when a C core is driven to zero and a negative potential is developed when the C core is driven to one. The converse is true of the one windings.

The voltage potentials shown on the sense lines exist if the code pattern 01 is applied from D-1 and D-0. A+2E fixed bias is applied on the bias line BL, although ground or another bias may be applied.

The common lines from D-1 and D-0 drive B-1 and B-0, so that E potentials are induced on the bias line BL, which are subtractive from the fixed bias, regardless of the applied code configuration. In this case, the potentials on the line BL at various points are as shown in parenthesis and the net bias applied to the sense lines at the juncture J is zero.

With a zero net bias at J, only the...