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Bidirectional Counter Stage

IP.com Disclosure Number: IPCOM000098510D
Original Publication Date: 1960-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Norton, DE: AUTHOR

Abstract

This fast counter stage provides addition or subtraction carry pulses with only one logical level delay per stage. With the circuit in a 0 condition, OR gate 1 is off and a signal is present on its a line 2 which is an input to AND gates 3 and 4. On receipt of an X (Add) or Y (subtract) pulse, the AND gate 3 or 4 turns on and applies a signal on output line 5 or 6. Both are inputs to OR gate 7. The output line 9 of gate 7 is the stage count indication and now indicates a 1 . The output of gate 7 is also one input of AND gate 8 whose other inputs are the X and Y signals and whose output line 10 is an input to OR gates 1 and 7. When the X or Y signal drops, gate 8 turns on to hold OR gate 7 on and turn on gate 1. This action drops the a signal on line 2 and puts a signal on line 11, an input of AND gates 12 and 13.

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Bidirectional Counter Stage

This fast counter stage provides addition or subtraction carry pulses with only one logical level delay per stage. With the circuit in a 0 condition, OR gate 1 is off and a signal is present on its a line 2 which is an input to AND gates 3 and
4. On receipt of an X (Add) or Y (subtract) pulse, the AND gate 3 or 4 turns on and applies a signal on output line 5 or 6. Both are inputs to OR gate 7. The output line 9 of gate 7 is the stage count indication and now indicates a 1 . The output of gate 7 is also one input of AND gate 8 whose other inputs are the X and Y signals and whose output line 10 is an input to OR gates 1 and 7. When the X or Y signal drops, gate 8 turns on to hold OR gate 7 on and turn on gate 1. This action drops the a signal on line 2 and puts a signal on line 11, an input of AND gates 12 and 13.

A second pulse received on the X or Y lines turns on an AND gate 12 or 13 to apply a signal to one of the output lines 14 or 15. Both 14 and 15 are inputs to OR gate 1 and keep 1 turned on when the signal on line 10 drops. Gate 7 turns off to induce the return of the stage to 0 and drops line 9 to hold gate 8 off.

Line 14 is energized when the stage is at 1 and an add signal is received. Line 14 and its complement line 16 are the Add carry X and X inputs to the next stage. Line 6 signals when a subtract Y signal is received with the stage at 0 . Line 6 and its complement line 17 are the subtract carry inputs Y and Y to the nex...