Browse Prior Art Database

Data Latch

IP.com Disclosure Number: IPCOM000098515D
Original Publication Date: 1960-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Homan, ME: AUTHOR

Abstract

The data latch is used to hold the voltage level of data signal line 5 constant for a period of time and not subject to variations at the terminal 6. The level line 5 is held constant during the interval that a latch control signal is applied to terminal 7.

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Data Latch

The data latch is used to hold the voltage level of data signal line 5 constant for a period of time and not subject to variations at the terminal 6. The level line 5 is held constant during the interval that a latch control signal is applied to terminal 7.

When a data signal is present, indicated by the 1 at terminal 6, and a latch signal is present, indicated by the 1 at terminal 7, the outputs of converter 8, AND 9 and AND 10 are as shown, 0 representing the absence of a signal. The 1 signal from the non inverted output of AND 10 is fed back through line 11 to converter 8, latching 8... 10 in the state as shown. The clamping transistor 12 absorbs excess current and holds the data signal at the 1 level. This is determined by the 1 level applied to its base by the 1 signal from the inverted output of AND 9. Should the level at 6 begin to drop, transistor 12 ceases to absorb excess current. Current from AND 10 maintains line 5 at the 1 level. This condition remains until the latch signal at 7 is removed and the output signal from AND 10 drops to the 0 level and stops supplying current.

When the signal on 6 is absent and latch signal on 7 is applied, the outputs from 8...10 are the reverse of the condition shown. The 0 level signal from the inverted output of AND 9 activates transistor 12 to clamp feedback line 11 to the 0 level. With the latch now set in the reverse state, should the level at terminal 6 tend to rise above the 0 level, the activated tra...