Browse Prior Art Database

Pulsing Magnetic Matrices

IP.com Disclosure Number: IPCOM000098518D
Original Publication Date: 1960-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Andrews, CA: AUTHOR

Abstract

This circuit insures coincidence of pulses supplied to a matrix such as the decoder matrix shown.

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Pulsing Magnetic Matrices

This circuit insures coincidence of pulses supplied to a matrix such as the decoder matrix shown.

Initially, the decoder cores 1,2,3,4 are in the negative remanence state. A two core per bit register 5,6, 7,8, which may be a buffer register, is provided to supply one voltage pulse per bit position at corresponding sense windings 9, 10, 11, 12. This action is approximately simultaneous, when the information in the register is read out by a pulse on the line 13.

Each of the register sense windings is connected in the emitter base circuit of a corresponding transistor, the collector circuit of which provides the input to the decoder matrix from the corresponding register core. For insuring that these inputs to the decoder are simultaneous, the two decoder input lines 14,15 from the first bit position are connected in a parallel pair which is in series with the parallel pair formed by the decoder input lines 16, 17 from the next bit position.

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