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Clamped Oscillator

IP.com Disclosure Number: IPCOM000098553D
Original Publication Date: 1959-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Halpern, P: AUTHOR

Abstract

The circuit permits a square wave pulse output to be turned on on off with a minimum of delay

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Clamped Oscillator

The circuit permits a square wave pulse output to be turned on on off with a minimum of delay

The +6 volts in series with the 1 K resistor provides a constant current source feeding the emitters of PNP junction transistors T(1), T(2) and T(3). As long as the input line is more negative than the bases of T(1) and T(3), transistor T(2) conducts all the current from the constant current source. This is the OFF condition of the oscillator. NPN transistor T(4), whose base-emitter junction is connected across the common collector load resistance of T(1) and T(2), conducts during the OFF time.

When the input potential is made positive, T(2) is cut off and current flow from the constant current source is switched to T(3), producing a positive going voltage step on the output line. At the same instant, T(4) is cut off, because of cessation of current through the common collector load resistance, and a positive going voltage step appears at the collector of T(4). This voltage step traverses the lumped constant delay line, is reflected and reversed in phase, and after a time equal to twice the delay, of the line is applied as a negative going voltage step to the base of T(1). This causes current to be switched from T(3) to T(1), resulting in a negative going voltage step at the output of T(3). Conduction through T(1) renders T(4) conductive again, dropping its collector potential. This drop is reversed in phase and applied, after delay, as a positive goin...