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Shift Register

IP.com Disclosure Number: IPCOM000098556D
Original Publication Date: 1959-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Lawrence, WW: AUTHOR

Abstract

The circuit forms a one core per bit shift register employing transistor amplifiers between stages to provide power gain.

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Shift Register

The circuit forms a one core per bit shift register employing transistor amplifiers between stages to provide power gain.

Assuming core 1 to be in a 1 state, a drive pulse from the A driver resets core 1 to 0. The output voltage induced in the secondary winding charges the temporary storage capacitor through the diode. A negative bias from the bias gate, which is applied for the duration of the A pulse, prevents the transistor from conducting. At the termination of the A pulse, the gate bias is removed and the capacitor voltage turns on the transistor to set core 2 to a 1. The capacitor discharges through the base-emitter junction of the transistor and is ready for the next A pulse. The width of the output pulse is determined by the values of capacity and forward resistance drop of the base-emitter junction of the transistor.

Since a power gain is achieved through the transistor, only, small amounts of energy need be stored in the capacitor and a small capacitor can be used. This reduces the loading in the output winding circuit of the core and reduces the power required to reset it. Thus, the power requirement of the A driver is substantially reduced.

PNP transistors may be used with suitable reversal of polarities.

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