Browse Prior Art Database

Electronic Circuit Error Detection

IP.com Disclosure Number: IPCOM000098570D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Johnson, OW: AUTHOR

Abstract

Multiple adjacent errors may be detected in addition to random single error detection and correction and double error detection in binary information transfer. Assuming each word is composed of information bits designated M and check bits designated K, the maximum number of information bits which may be checked by K check bits according to the redundancy code shown in U.S. Patent 2, 552, 629 is (2/K-l/-K). Assuming a 12 bit word to be checked, one conventional arrangement for single error detection and correction and double error detection would be: K(1)K(2)K(3)M(1)K(4)M(2)M(3)M(4)K(5)M(5)M(6)M(7)

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Electronic Circuit Error Detection

Multiple adjacent errors may be detected in addition to random single error detection and correction and double error detection in binary information transfer.

Assuming each word is composed of information bits designated M and check bits designated K, the maximum number of information bits which may be checked by K check bits according to the redundancy code shown in U.S. Patent 2, 552, 629 is (2/K-l/-K). Assuming a 12 bit word to be checked, one conventional arrangement for single error detection and correction and double error detection would be: K(1)K(2)K(3)M(1)K(4)M(2)M(3)M(4)K(5)M(5)M(6)M(7)

Each information and check bit in the word is assigned a unique position number, one example being shown by Table I. Each position number contains K-1 binary digits making possible 2/K-1/ position numbers for each word. Each position number corresponds to the parity subgroup for single error correction, described in U.S.

Patent 2,552, 629. For triple adjacent error detection, the Zones are defined such that Zone 1 contains all bits with position numbers containing 00 in the two highest order bit positions, Zone #2 contains corresponding bit positions 01, zone #3 contains corresponding bit positions 10, and Zone #4 contains corresponding bit positions 11. Therefore all triple errors involving a single bit from each of Zones 1, 2 and 3 affect the parity checks such that it appears to be a single error in a bit of Zone #4.

SEE TABLE IN PA...