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CTRL Latch

IP.com Disclosure Number: IPCOM000098576D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Flynn, MJ: AUTHOR

Abstract

The latch utilizes Complemented Transistor Resistor Logic circuits. With the initial inputs to blocks 1 and 2 both positive (solid lines), the PNP transistors are non-conducting and their collector potentials are negative. This negative potential is applied as input to block (3), where it maintains the NPN transistor non-conducting. Block 3 establishes a positive potential on its output line, which is fed back to the input of block 1 to latch it in its non-conducting condition. Such action in turn latches the output line at a positive potential. To switch the circuit to its other condition, the input to block 2 is made negative, its transistor conducts and its output line rises to ground. Now the NPN transistor conducts and the output line drops to ground.

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CTRL Latch

The latch utilizes Complemented Transistor Resistor Logic circuits. With the initial inputs to blocks 1 and 2 both positive (solid lines), the PNP transistors are non-conducting and their collector potentials are negative. This negative potential is applied as input to block (3), where it maintains the NPN transistor non-conducting. Block 3 establishes a positive potential on its output line, which is fed back to the input of block 1 to latch it in its non-conducting condition. Such action in turn latches the output line at a positive potential. To switch the circuit to its other condition, the input to block 2 is made negative, its transistor conducts and its output line rises to ground. Now the NPN transistor conducts and the output line drops to ground. The feedback arrangement then turns on the transistor of block 1 to latch the circuit. :AB As shown by the dotted lines, multiple inputs can be supplied to each block. It is then necessary that all inputs to a PNP transistor be negative to render it conductive and all inputs to an NPN transistor be positive to render it conductive. Therefore, various combinations of input conditions can be selected for each condition of the output line.

A latch can be constructed with opposite transistor types and with suitable polarity reversals.

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