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Browse Prior Art Database

CTRL Adder

IP.com Disclosure Number: IPCOM000098577D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Flynn, MJ: AUTHOR

Abstract

The full adder utilizes Complemented Transistor Resistor Logic circuits.

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CTRL Adder

The full adder utilizes Complemented Transistor Resistor Logic circuits.

Each of the AND blocks comprises a transistor having both collector and base returned to the same polarity source and each of the inputs coupled to the base through a resistor. In the case of the NPN blocks shown, when all three inputs are up, the transistor conducts and the output line drops to give the AND function. Complementary logic results when PNP blocks are used. The OR function is provided by connecting the collectors in common. The block I is a non-translating inverter to provide the NOT CARRY output.

The arrangement shown uses eight transistors and requires only one stage of delay to perform full addition.

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