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IP.com Disclosure Number: IPCOM000098578D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Flynn, MJ: AUTHOR

Abstract

The circuit utilizes Complemented Transistor Resistor Logical blocks and a binary trigger to perform the addition function.

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Change Adder

The circuit utilizes Complemented Transistor Resistor Logical blocks and a binary trigger to perform the addition function.

Initially, the binary trigger is set to 0 . Blocks 1 and 2 form an EXCLUSIVE OR circuit. Signals to be added are applied successively to the terminals marked INPUT . During the first cycle of operation, the first signal and the carry are supplied to the blocks. If either is a 1 , an output is provided to switch the trigger to a 1 . If both are 1 , the trigger remains at 0 and block 4 provides a 1 at its carry output. During the second cycle, the second signal is applied to the input terminals. If it is a 1, the state of the trigger is changed; if it is a 0 the circuit remains unchanged . The carry is generated by block (3), when the second input signal is a 1 and the trigger is already in the 1 state.

Each of the blocks comprises a transistor having both base and collector returned to the same polarity voltage. This permits both the AND and OR function to be performed with but one level of delay. The inverter is a single input, non-translating block and the trigger may be of any suitable type.

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