Browse Prior Art Database

Magnetic OR Device

IP.com Disclosure Number: IPCOM000098583D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Butler, SA: AUTHOR

Abstract

The high speed magnetic core logical OR device employs a two phase clock drive and transfer circuits which include a series capacitor C. If S(1a) or S(1b) is in the 1 state upon energization of the A shift windings, the one S(1) core is reset to 0 and provides a counter-clockwise current in its associated loop which simultaneously charges C(1a) or C(1b), respectively, and switches K(2a) or K(2b) to the 1 state. The core K(2a) or K(2b) in switching provides a clockwise current in the output loop to charge C(2). When the rate of switching of K(2a) or K(2b) starts decreasing, the capacitor C(1) or C(1b) discharges to provide a clockwise current in its associated loop while simultaneously the capacitor C(2) discharges to provide a counter-clockwise current in the output loop.

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Magnetic OR Device

The high speed magnetic core logical OR device employs a two phase clock drive and transfer circuits which include a series capacitor C. If S(1a) or S(1b) is in the 1 state upon energization of the A shift windings, the one S(1) core is reset to 0 and provides a counter-clockwise current in its associated loop which simultaneously charges C(1a) or C(1b), respectively, and switches K(2a) or K(2b) to the 1 state. The core K(2a) or K(2b) in switching provides a clockwise current in the output loop to charge C(2). When the rate of switching of K(2a) or K(2b) starts decreasing, the capacitor C(1) or C(1b) discharges to provide a clockwise current in its associated loop while simultaneously the capacitor C(2) discharges to provide a counter-clockwise current in the output loop. Since an energy loss takes place when the core K(2) or K(2b) is initially switched, C(2) in discharging provides a lesser current so that the core K(2a) or K(2b) is reset to 0 and the core S(2) is switched to the 1 state. :AB Circuit operation is similar when both S(1a) and S(1b) are in the 1 state upon energization of the A shift windings, since the energy loss accompanying transfer through the cores K(2a) and K(2b) is again utilized to reset the cores to 0 and to switch the core S(2) to 1.

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