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Magnetic AND Device

IP.com Disclosure Number: IPCOM000098585D
Original Publication Date: 1959-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Butler, SA: AUTHOR

Abstract

The high speed magnetic core AND device employs a two-phase clock drive and transfer circuits including a series capacitor. With one of the cores S(1a) or S(1b) in the 1 state, upon energization of the A shift windings S(1a) or S(1b) is reset to 0 to provide a counter-clockwise current in its associated circuit which tends to switch K(2a) or K(2b) to the 1 state, but due to the combined loading of C(2a), C(2b), K(2a) or K(2b), the core which is not impulsed at this time, and C(1a) or C(1b), switching is prevented.

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Magnetic AND Device

The high speed magnetic core AND device employs a two-phase clock drive and transfer circuits including a series capacitor. With one of the cores S(1a) or S(1b) in the 1 state, upon energization of the A shift windings S(1a) or S(1b) is reset to 0 to provide a counter-clockwise current in its associated circuit which tends to switch K(2a) or K(2b) to the 1 state, but due to the combined loading of C(2a), C(2b), K(2a) or K(2b), the core which is not impulsed at this time, and C(1a) or C(1b), switching is prevented.

If both S(1a) and S(1b) are in the 1 state and the A shift windings are energized, S(1a) and S(1b) are reset to 0 and provide a counter clockwise current in both input loops which switch K(2a) and K(2b) to 1, respectively, since the output circuit is now symmetrical, and simultaneously, the capacitors C(1a), C(1b), C(2a) and C(2b) are charged. When the rate of switching of K(2a) and K(2b) starts decreasing, C(1a) and C(1b) discharge to provide a clockwise current in each input loop which tends to reset K(2a) and K(2b) to 0.

Simultaneously, C(2a) and C(2b) discharge to provide a counter clockwise current which tends to switch K(2a) and K(2b) and S(2a) and S2b to the 1 state. Since C(1a) and C(1b) were previously charged to a greater degree than the respective capacitors C(2a) and C(2b) due to losses accompanying transfer of energy through K(2a) and K(2b), the K(2) cores are reset to 0 and the S(2) cores are switched to 1.

Thus upon en...