Browse Prior Art Database

Magnetic Core Decimal Counter

IP.com Disclosure Number: IPCOM000098615D
Original Publication Date: 1959-Jun-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Lee, TL: AUTHOR [+3]

Abstract

The counter utilizes five bistable magnetic core shifting circuits of the one-core-per-bit type for decimal counting. The cores A-E are initially set to the condition shown in the 0 column of the counting sequence chart by energizing the reset line 2. The carry core is also reset to 0. Pulses to be counted are delivered to the drive line 3. The drive pulses switch all cores to 0. Those formerly at 1 experience flux reversal and provide an output of a polarity to pass the diodes. These output pulses are temporarily stored by the capacitors and delivered to the input windings of succeeding cores between drive pulses. The output pulse derived when core A switches from 1 to 0 drives both cores A and B to 1. The output of core B drives core C and the carry core to 1. The output of core C drives cores A to D to 1.

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Magnetic Core Decimal Counter

The counter utilizes five bistable magnetic core shifting circuits of the one- core-per-bit type for decimal counting. The cores A-E are initially set to the condition shown in the 0 column of the counting sequence chart by energizing the reset line 2. The carry core is also reset to 0. Pulses to be counted are delivered to the drive line 3. The drive pulses switch all cores to 0. Those formerly at 1 experience flux reversal and provide an output of a polarity to pass the diodes. These output pulses are temporarily stored by the capacitors and delivered to the input windings of succeeding cores between drive pulses. The output pulse derived when core A switches from 1 to 0 drives both cores A and B to 1. The output of core B drives core C and the carry core to 1. The output of core C drives cores A to D to 1. The output of core D drives core E to 1. The output of core E drives core A and the carry core to 0. The carry core is set to 1 only when core B is driven from 1 to 0 and core E is driven from 0 to 0. This condition exists only upon the application of every tenth drive pulse.

The advantages of this circuit reside in the fact that the inverter stage normally necessary in five stage magnetic core decimal counters is not needed, and in the fact that the impedance seen by the driver remains substantially constant throughout the counting sequence.

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