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Browse Prior Art Database

High Speed Core Memory

IP.com Disclosure Number: IPCOM000098653D
Original Publication Date: 1959-Aug-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Booth, RR: AUTHOR

Abstract

In magnetic core storage systems employing coincident current selection methods with conventional driving current amplitudes, a major limiting factor controlling memory cycle times and, hence, memory speed, has been the time required to switch a core from one magnetic state to the other. In the two dimensional memory shown, this time has been reduced, and cycle time shortened, by employing partial switching during writing operations.

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High Speed Core Memory

In magnetic core storage systems employing coincident current selection methods with conventional driving current amplitudes, a major limiting factor controlling memory cycle times and, hence, memory speed, has been the time required to switch a core from one magnetic state to the other. In the two dimensional memory shown, this time has been reduced, and cycle time shortened, by employing partial switching during writing operations.

The vertical columns of cores in the partial matrix represent word storage locations, and the rows represent bit positions. A separate word write line 10 and write driver 11 are provided for each column. A separate bit line 12 and bit driver 13 are provided for each row. The write and bit drivers are adjusted to provide currents of normal halfselect amplitude. A word is written in memory by coincidently energizing a write line and one or more bit lines to develop only in the cores at the intersections of the selected bit lines and the selected write line, a magnetic force greater than the coercive force of the core. Words are read out of memory by applying full-select current pulses to word read lines 14 coupled to the cores of each column. Word read drivers 15 are provided for each read line
14.

During the write operation, the write and bit driving pulses are shortened so that the driving force applied to the selected cores is terminated before the cores have fully switched. The selected cores are only partial...