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Register Zero Test

IP.com Disclosure Number: IPCOM000098688D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Cochrane, HW: AUTHOR

Abstract

Multi-order registers in tabulating or computing machines store decimal digital information, each register containing a decimal counter for each order. These machines have circuitry for testing for the presence of zero,s or non-zero's stored in a register, the result of the test being used to control either some special machine function or the next operation to be performed by the tabulator or computer.

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Register Zero Test

Multi-order registers in tabulating or computing machines store decimal digital information, each register containing a decimal counter for each order. These machines have circuitry for testing for the presence of zero,s or non-zero's stored in a register, the result of the test being used to control either some special machine function or the next operation to be performed by the tabulator or computer.

Where core matrix adders are utilized for each digital position, extremely rapid and simple zero tests can be effected. To perform the zero test, the register to be tested, which may be the addend register, is added to a zero valued augend from the augend register. The core matrix adder preferred is one in which the addend is entered in one direction to set a row of cores in the matrix, and the augend is subsequently entered from another direction to reset a column of cores. An output is then available from the single core at the intersection of the two drives which is representative of the digit sum of the two.

A special sense winding links all the cores representative of the sum of zero in the augend and any digit other than zero in the addend. Thus, an output on the zero test sense line from a core matrix adder for one order indicates that the addend digit is some value other than zero. This zero test winding is linked serially through all digits of the core matrix adder to indicate a non-zero balance in the complete register.

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