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Transfer Pulse Amplifier Error Check

IP.com Disclosure Number: IPCOM000098690D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Dantonio, RA: AUTHOR

Abstract

The apparatus is common to first and second chains of serially-connected pulse amplifiers 1-3 and 4-6, respectively. It is effective to produce signals at appropriate ones of alarm terminals 10, 11, and 12 in the event that either or both of a particular pair of pulse amplifiers fails to produce signals.

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Transfer Pulse Amplifier Error Check

The apparatus is common to first and second chains of serially-connected pulse amplifiers 1-3 and 4-6, respectively. It is effective to produce signals at appropriate ones of alarm terminals 10, 11, and 12 in the event that either or both of a particular pair of pulse amplifiers fails to produce signals.

Input pulses are sequentially applied to terminals 8 and 9 and normally are passed through amplifiers 1-3 and 4-6, respectively. Such pulses also are passed through OR circuit 13 and delay line 14. Output pulses from either one of each pair of amplifiers, such as 1 and 4, also are passed through OR circuit 18 to shift flip flop 15 to its 1 state, so that the pulse from delay line 14 arriving at gate 19 is blocked from passage to terminal 10. This pulse shifts flip-flop 15 back to its 0 state. If, however, pulse amplifier 1 has failed so that flip flop 15 is allowed to remain in its 0 state, the pulse from delay line 14 finds gate 19 conditioned to pass that impulse to alarm terminal 10. The other flip flops 16 and 17 and gates 20 and 21 operate similarly with respect to the other pairs of pulse amplifiers in the chains.

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