Browse Prior Art Database

Core Driver Error Check

IP.com Disclosure Number: IPCOM000098691D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Riley, A: AUTHOR

Abstract

This apparatus is for actuating alarm 42 upon the failure of core driver 33 to switch cores 2-8 of register 10. Flip-flop 21 initially is set to 0 by a pulse externally applied to reset conductor 25. Core 1 is also reset at this time. The subsequent operation of contacts 31 causes pulse generator 29 to apply an impulse to core driver 33 and delay unit 35. Core driver 33 applies a pulse to the serially-arranged read windings of cores 2-8 and core 1. This pulse is assumed to be sufficient, if core 1 is switched. If the signal from core driver 33 is sufficient, the resulting output signal from core 1 complements flip-flop 21, to decondition gate 39. The pulse from delay unit 35 thin appears at gate 39, where its passage is blocked.

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Core Driver Error Check

This apparatus is for actuating alarm 42 upon the failure of core driver 33 to switch cores 2-8 of register 10. Flip-flop 21 initially is set to 0 by a pulse externally applied to reset conductor 25. Core 1 is also reset at this time. The subsequent operation of contacts 31 causes pulse generator 29 to apply an impulse to core driver 33 and delay unit 35. Core driver 33 applies a pulse to the serially-arranged read windings of cores 2-8 and core 1. This pulse is assumed to be sufficient, if core 1 is switched. If the signal from core driver 33 is sufficient, the resulting output signal from core 1 complements flip-flop 21, to decondition gate 39. The pulse from delay unit 35 thin appears at gate 39, where its passage is blocked. The signal from delay unit 35 also is passed through delay unit 43 and OR circuit 27 to reset flip-flop 21 to 0 .

If core driver 33 fails to provide an output signal sufficient to switch core 1, flip flop 21 continues in its 0 state. When the aforementioned pulse from delay unit 35 appears at the input of gate 39, it is passed through that gate to alarm 42.

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