Browse Prior Art Database

High Speed Two Dimensional Memory Array

IP.com Disclosure Number: IPCOM000098710D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Councill, ED: AUTHOR

Abstract

The drawing illustrates a wiring arrangement for a two dimensional coincident current magnetic core memory array designed for noise free high speed operation.

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High Speed Two Dimensional Memory Array

The drawing illustrates a wiring arrangement for a two dimensional coincident current magnetic core memory array designed for noise free high speed operation.

Inductive coupling between the horizontal bit lines is reduced by arranging each bit line 10 in the form of a closed loop lying in the plane of the array. As shown, alternate columns of the memory cores 11 are staggered so that corresponding cores in adjacent columns lie in two separate rows. Each bit line passes in one direction through one row and returns in the other direction through the other row. Current flowing in a bit line sets up two opposing fields which cancel, thus materially reducing mutual inductance between adjacent lines.

By arranging the cores of each bit storage position in two rows it is also possible to reduce sense line noise. Since each sense line couples two rows of cores, a figure 8 pattern may be used to provide cancellation of half-select noise during write operations and to provide cancellation of electrostatic noise between the bit and sense lines..

Full-select magnetomotive force for reading words stored in the array is obtained by threading the read lines 13 (only one of,which is shown in full) twice through each core and employing read drivers which produce half-select current.

While the drawing shows only a small array, it will be understood that it may be expanded to any desired size. A large array may be compacted by folding the colu...