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Full Adder

IP.com Disclosure Number: IPCOM000098716D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Ward, RL: AUTHOR

Abstract

A matrix 1 is provided comprising N/2/ bistable magnetic cores where N is the system radix. The matrix has N first input lines A and N second input lines B. The even and odd drive lines of the inputs A and B are independently bussed to provide drive input lines A (even), A bar (odd), B underscore (even), and B bar (odd). The individual input drives A underscore, A bar, B underscore~ B bar, are applied to a carry logic stage 3, an even logic stage 4, an odd logic stage 5, and are also bussed together and applied through a line 6 to a carry driver stage 7.

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Full Adder

A matrix 1 is provided comprising N/2/ bistable magnetic cores where N is the system radix. The matrix has N first input lines A and N second input lines B. The even and odd drive lines of the inputs A and B are independently bussed to provide drive input lines A (even), A bar (odd), B underscore (even), and B bar (odd). The individual input drives A underscore, A bar, B underscore~ B bar, are applied to a carry logic stage 3, an even logic stage 4, an odd logic stage 5, and are also bussed together and applied through a line 6 to a carry driver stage 7.

An output line 8 is provided from the carry logic stage 3, through matrix 1 and a line 9 to a delay stage 10. The delay stage 10 is connected to the carry driver stage 7 which has an output line 11 directed to the logic stages 3, 4, and 5. The matrix 1 is provided with N sense digit lines 12. One side of the even sense digit lines 12 is bussed to an output line 13 of the odd logic stage 5, whereas one side of the odd sense digit lines 12 is bussed to an output line 14 of the even logic stage 4.

When digit inputs are applied to both an A and a B input drive line, the matrix 1 provides an output pulse on two of the sense digit lines 12, one of which corresponds to the true sum of the input digits A and B, while the other corresponds to the next higher digit.

One of the two output signals on the sense digit lines 12 is selected by providing a cancelling pulse on the other through either the line 13 from t...