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Browse Prior Art Database

Binary Trigger

IP.com Disclosure Number: IPCOM000098721D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Miano, SV: AUTHOR [+2]

Abstract

The circuit illustrated operates binarywise using only six transistors and a delay.

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Binary Trigger

The circuit illustrated operates binarywise using only six transistors and a delay.

Assuming that the trigger is ON (i. e., the ON output is up and the OFF output is down), T(5) is biassed off and T(4), whose base is grounded, conducts. The collector of T(4) is connected through a pulse forming network, D(1), L(1), R(1) to the base of T(3), rendering the latter conductive. conductive. With T(3) conducting, T(2) is held nonconductive. T(1) is biassed to be normally off and during this time is nonconductive.

When a positive pulse is applied at the input terminal, T(1) is rendered conductive, dropping its collector potential towards a negative value. This back biases the emitter base diode of T4 to turn it off. T(5) remains nonconducting. The negative level now at the collector of T(4) turns off T(3), to cause T(2) to become conductive. The down level now at the collector of T(2) conditions T(5) to conduct at the cessation of the input pulse. Elements L(3), D(3) maintain T(1) conductive long enough to permit T(2) to switch and condition T(5).

At the termination of conduction of T(1), T(5) is rendered conductive to maintain T(4) nonconducting and T(2) conducting. The trigger has now been switched to its OFF state. The pulse formed by D(1), L(1), and R(1) must be of sufficient duration to hold T(3) nonconducting until T(1) is turned off and T(5) turned on. A similar pulse forming network, D(2), L(2), R(2), is provided at the base of T(2) and the next in...