Browse Prior Art Database

Parity Gate Circuit

IP.com Disclosure Number: IPCOM000098725D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Lovallo, FJ: AUTHOR

Abstract

This circuitry combines the 0 or 1 output of flip flop 3 with parity status signals from the preceding flip-flops in order to produce an appropriate signal at terminal 4 or 5.

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Parity Gate Circuit

This circuitry combines the 0 or 1 output of flip flop 3 with parity status signals from the preceding flip-flops in order to produce an appropriate signal at terminal 4 or 5.

Assume that flip-flop 3 is in 1 condition. Current then flows from -9.5v. through resistor 6, the bias windings of cores 7 and 8, and diode 9 to the l output of flip-flop 3, but not through the bias windings of cores 10 and 11 because diode 12 is back-biased at this time. Reset current always flows from -9.5v. through resistor 13 and the reset windings of cores 11, 8, 7, and 10 to ground. A pulse appearing on odd input terminal 1 is applied to cores 8 and 11. Core 8 is biased beyond switching by the current in its reset and bias windings. Therefore, only core 11 is switched and produces an output pulse. This pulse turns on transistor
14. The resulting pulse through the transistor 14 emitter-collector circuit is passed to even output terminal 5. Core 11 is thereafter reset by the aforementioned reset current. Other combinations of input signals on terminals 1 and 2 and the outputs of flip-flop 3 produce appropriate impulses at terminals 4 and 5.

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