Browse Prior Art Database

Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000098728D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Henle, RA: AUTHOR

Abstract

An exclusive OR circuit is provided including four transistors 1, 2, 3 and 4, two inputs 5 and 6 and two outputs 7 and 8. ON (+) and OFF (-) inputs to both terminals 5 and 6 establish terminal 7 at the ON (+) level and terminal 8 at the OFF (-) level. An OFF signal at one terminal 5 or 6 coincident with an ON signal at the other, establishes terminal 7 at the OFF level and terminal 8 at the ON level.

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Exclusive OR Circuit

An exclusive OR circuit is provided including four transistors 1, 2, 3 and 4, two inputs 5 and 6 and two outputs 7 and 8. ON (+) and OFF (-) inputs to both terminals 5 and 6 establish terminal 7 at the ON (+) level and terminal 8 at the OFF (-) level. An OFF signal at one terminal 5 or 6 coincident with an ON signal at the other, establishes terminal 7 at the OFF level and terminal 8 at the ON level.

When both terminals 5 and 6 receive identical inputs (ON or OFF), transistors 1 and 2 conduct substantially the same amount in parallel paths from source 9 through transistors 1 and 2, circuits 10 and 11 and batteries 12 and 13.

When terminal 5 is ON and 6 is OFF, or 5 is OFF and 6 is ON, the transistor 1 or 2 which receives the OFF signal impresses the negative potential from its emitter (2E or 1E) to the base of transistor 3 or 4, reverse biasing the emitter- base impedance of the transistor 1 or 2 which is receiving the ON signal, to cut that transistor off.

The current which previously flowed from the now cut off transistor through wire 14 now flows through wire 15 and circuits 16 and 17 to batteries 12 and 13. Also, current flow through circuit 11 is reversed, terminal 8 assumes the ON level and terminal 7 assumes the OFF level.

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