Browse Prior Art Database

Counter Failure Detector

IP.com Disclosure Number: IPCOM000098734D
Original Publication Date: 1959-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Arneth, P: AUTHOR

Abstract

In a binary counter comprising flip-flops 1, 2, 3 and 4 and associated carry gates 5, 6, 7 and 8, application of a pulse to input conductor 9 causes one stage of the counter to be set in the 1 state and all lower orders of the counter to the 0 state. Pulse generators 10, 11, 12 and 13 respond to the transition of the associated flip flops to apply signals through conductors 14, 15, 16 and 17 to AND circuits 18, 19 and 20 and to OR circuit 21. Pulse generators 22, 23 and 24 respond to the transition of flip flops 1 through 4 to the 0 state to apply signals to AND circuits 18, 19 and 20, respectively.

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Counter Failure Detector

In a binary counter comprising flip-flops 1, 2, 3 and 4 and associated carry gates 5, 6, 7 and 8, application of a pulse to input conductor 9 causes one stage of the counter to be set in the 1 state and all lower orders of the counter to the 0 state. Pulse generators 10, 11, 12 and 13 respond to the transition of the associated flip flops to apply signals through conductors 14, 15, 16 and 17 to AND circuits 18, 19 and 20 and to OR circuit 21. Pulse generators 22, 23 and 24 respond to the transition of flip flops 1 through 4 to the 0 state to apply signals to AND circuits 18, 19 and 20, respectively.

The output from each of the AND circuits 18, 19 and 20 indicates the transition of one stage of the counter to the 1 state and the transition of the next lower stage to the 0 state. These output signals are then applied through OR circuit 21 to gate 25 which inhibits alarm circuit 26. In the absence of an output from OR circuit 21, gate circuit 25 conditions the alarm circuit 26, which is actuated upon receipt of the next count pulse.

If both sides of a flip flop 1, 2, 3 or 4 are up, due to a failure, OR circuit 27 is actuated through gates 28, 29, 30 and 31 to actuate the alarm 26 indicating failure of the binary counter.

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